HIGHLIGHTS
  • Research
    ISSCC 2016 CNN Chip Featured in IEEE Spectrum April 2016 Issue
  • Award
    2014 IDEC SoC Congress Chip Design Contest Best Design Award
  • Award
    The 32nd IEEE ICCD Best Paper Award
  • Research
    A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth
  • Award
    HPCA 2014 Best Paper Runner-Up

Our Convolutional Neural Network(CNN) chip presented at ISSCC 2016 is covered in the article "Neural Networks on the Go" in the IEEE Spectrum April 2016 Issue.

Related paper: "A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems" by Jaehyeong Sim

Yong-Hun Kim, Young-Ju Kim, and Tae-Ho Lee (Advisor Lee-Sup Kim) received “Best Design Award” in 2014 IDEC SoC Congress Chip Design Contest.

Related paper: "A 21Gb/s, 1.63pJ/bit Adaptive CTLE and 1-tap DFE with Single Loop Spectrum Balancing Method in 65nm CMOS" by Yong-Hun Kim

Jaehyeong Sim, Jun-Seok Park, and Seungwook Paek (Advisor Lee-Sup Kim) received “Best Paper Award” in The 32nd IEEE International Conference on Computer Design.

Related paper: "Timing Error Masking by Exploiting Operand Value Locality in SIMD Architecture" by Jaehyeong Sim

A source synchronous architecture with constant and wide jitter-tracking bandwidth (JTB) is presented. The proposed receiver is based on an injection-locked oscillator (ILO), which provides jitter filtering and phase deskew simultaneously. While using only the ILO has intrinsic two dependence problems (JTB versus deskew and JTB versus a voltage-controlled oscillator tuning range required for 1 unit interval deskew), the proposed receiver makes them independent. Therefore, the proposed receiver can achieve the optimal JTB in a wide range by controlling deskew phase and JTB independently. A test chip was implemented to prove 11Gb/s data recovery with constant 70MHz to 1GHz JTB in 0.13μm CMOS.

Related paper: "A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth" by Sang-Hye Chung

Wongyu Shin, Jeongmin Yang, and Jungwhan Choi (Advisor Lee-Sup Kim) received “Best Paper Runner-Up Award” in HPCA 2014.

Related paper: "NUAT: A Non-Uniform Access Time Memory Controller" by Wongyu Shin

Latest News

March 8, 2017

김현욱씨의 논문이 ACM/IEEE Design Automation Conference에 게재 승인 되었습니다.
.
Read More

Feb. 17, 2017

2017년 졸업식이 있었습니다.
.
Read More

Feb. 7, 2017

2017년 연구실 신입생 환영회 및 졸업생 송별회가 있었습니다.
.
Read More

Feb. 3, 2017

신원규씨의 논문이 TC에 게재 승인 되었습니다.
*제목: : Bank-Group Level Parallelism
Read More

Jan. 16, 2017

신원규씨의 논문이 TC에 게재 승인 되었습니다.
*제목: Rank-Level Parallelism in DRAM
Read More

Dec. 22, 2016

2016년 12월 22일 오전 11시에 김현욱씨의 석사학위 디펜스가 있습니다.
*주제: A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks
Read More

Dec. 21, 2016

최영재씨의 논문이 WACV 2017에 발표 승인 되었습니다.
*제목: Hardware-Centric Vision Processing for Mobile IoT Environment Exploiting Approximate Graph cut in Resistor Grid
Read More

Dec. 8, 2016

2016년 12월 8일 오후 4시에 최명훈씨의 석사학위 디펜스가 있습니다.
*주제: An Energy-Efficient Sparse Neuromorphic System with On-Chip Learning
Read More

Nov. 30, 2016

2016년 11월 30일 오후 4시에 김용훈씨의 박사학위 디펜스가 있습니다.
*주제: An Input Data and Clock Jitter Tolerant Digital CDR for LCD Intra-Panel Interface
Read More

Nov. 21, 2016

2016년 11월 21일 오후 2시에 신원규씨의 박사학위 디펜스가 있습니다
*주제: DRAM 레이턴시를 줄이기 위한 아키텍처 연구
Read More

Recently Accepted Papers

Conference (to be presented)

Yeongjae Choi, Jun-Seok Park, Lee-Sup Kim
Hardware-Centric Vision Processing for Mobile IoT Environment Exploiting Approximate Graph cut in Resistor Grid
IEEE Winter Conference on Applications of Computer Vision, 2017
 
Hyeonuk Kim, Jaehyeong Sim, Yeongjae Choi, Lee-Sup Kim
A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks
ACM/IEEE Design Automation Conference, 2017