- Award
2017 IDEC SoC Congress Chip Design Contest Best Design Award - Research
ISSCC 2016 CNN Chip Featured in IEEE Spectrum April 2016 Issue - Award
2014 IDEC SoC Congress Chip Design Contest Best Design Award - Award
The 32nd IEEE ICCD Best Paper Award - Research
A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth
Chong-soo Jung, Dong-il Lee and Dae-woong Lee(Advisor Lee-Sup Kim) received “Best Design Award” in 2017 IDEC SoC Congress Chip Design Contest.
Related paper: "A DLL-based Reference-less CDR with ISI Jitter Reduction Scheme "
by Chongsoo Jung
Our Convolutional Neural Network(CNN) chip presented at ISSCC 2016 is covered in the article "Neural Networks on the Go" in the IEEE Spectrum April 2016 Issue.
Related paper: "A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems"
by Jaehyeong Sim
Yong-Hun Kim, Young-Ju Kim, and Tae-Ho Lee (Advisor Lee-Sup Kim) received “Best Design Award” in 2014 IDEC SoC Congress Chip Design Contest.
Related paper: "A 21Gb/s, 1.63pJ/bit Adaptive CTLE and 1-tap DFE with Single Loop Spectrum Balancing Method in 65nm CMOS"
by Yong-Hun Kim
Jaehyeong Sim, Jun-Seok Park, and Seungwook Paek (Advisor Lee-Sup Kim) received “Best Paper Award” in The 32nd IEEE International Conference on Computer Design.
Related paper: "Timing Error Masking by Exploiting Operand Value Locality in SIMD Architecture"
by Jaehyeong Sim
A source synchronous architecture with constant and wide jitter-tracking bandwidth (JTB) is presented. The proposed receiver is based on an injection-locked oscillator (ILO), which provides jitter filtering and phase deskew simultaneously. While using only the ILO has intrinsic two dependence problems (JTB versus deskew and JTB versus a voltage-controlled oscillator tuning range required for 1 unit interval deskew), the proposed receiver makes them independent. Therefore, the proposed receiver can achieve the optimal JTB in a wide range by controlling deskew phase and JTB independently. A test chip was implemented to prove 11Gb/s data recovery with constant 70MHz to 1GHz JTB in 0.13μm CMOS.
Related paper: "A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth"
by Sang-Hye Chung
Latest News
Video
Demonstration video of object classification from 32x32 input images using our CNN chip.Demonstration viedo of image classification from 28 x 28 handwritten digit images using FPGA.
Recently Accepted Papers
Journal (to be published)
| Daewoong Lee, Dongil Lee, Yong-Hun Kim, Hyunkyu Jeon, Byungguk Kim, Lee-Sup Kim |
| A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE with Non-Time-Overlapping Data Generation for 4:1 CMOS Clockless Multiplexer |
| IEEE Transactions on Circuits and Systems II, 2019 |
| Chongsoo Jung, Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim |
| A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR with Super-Harmonic Injection-Locking in 65 nm CMOS |
| IEEE Transactions on Circuits and Systems II, 2019 |
| Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim |
| A 0.9-V 12-Gb/s 2-FIR Tap Direct DFE with Feedback-Signal Common-Mode-Control |
| IEEE Transactions on Very Large Scale Integration, 2018 |
| Jaemin Jang, Wongyu Shin, Jungwhan Choi, Yongju Kim, Lee-Sup Kim |
| Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory |
| IEEE Transactions on Computers, 2018 |
Conference (to be presented)
| Seungkyu Choi, Jaekang Shin, Yeongjae Choi, Lee-Sup Kim |
| An Optimized Design Technique of Low-Bit Neural Network Training for Personalization on IoT Devices |
| IEEE/ACM Design Automation Conference, 2019 |
| Hyeonuk Kim, Jaehyeong Sim, Yeongjae Choi, Lee-Sup Kim |
| NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks |
| IEEE International Symposium on High-Performance Computer Architecture, 2019 |
