HIGHLIGHTS
  • Award
    2017 IDEC SoC Congress Chip Design Contest Best Design Award
  • Research
    ISSCC 2016 CNN Chip Featured in IEEE Spectrum April 2016 Issue
  • Award
    2014 IDEC SoC Congress Chip Design Contest Best Design Award
  • Award
    The 32nd IEEE ICCD Best Paper Award
  • Research
    A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth
  • Award
    HPCA 2014 Best Paper Runner-Up

Chong-soo Jung, Dong-il Lee and Dae-woong Lee(Advisor Lee-Sup Kim) received “Best Design Award” in 2017 IDEC SoC Congress Chip Design Contest.

Related paper: "A DLL-based Reference-less CDR with ISI Jitter Reduction Scheme " by Chongsoo Jung

Our Convolutional Neural Network(CNN) chip presented at ISSCC 2016 is covered in the article "Neural Networks on the Go" in the IEEE Spectrum April 2016 Issue.

Related paper: "A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems" by Jaehyeong Sim

Yong-Hun Kim, Young-Ju Kim, and Tae-Ho Lee (Advisor Lee-Sup Kim) received “Best Design Award” in 2014 IDEC SoC Congress Chip Design Contest.

Related paper: "A 21Gb/s, 1.63pJ/bit Adaptive CTLE and 1-tap DFE with Single Loop Spectrum Balancing Method in 65nm CMOS" by Yong-Hun Kim

Jaehyeong Sim, Jun-Seok Park, and Seungwook Paek (Advisor Lee-Sup Kim) received “Best Paper Award” in The 32nd IEEE International Conference on Computer Design.

Related paper: "Timing Error Masking by Exploiting Operand Value Locality in SIMD Architecture" by Jaehyeong Sim

A source synchronous architecture with constant and wide jitter-tracking bandwidth (JTB) is presented. The proposed receiver is based on an injection-locked oscillator (ILO), which provides jitter filtering and phase deskew simultaneously. While using only the ILO has intrinsic two dependence problems (JTB versus deskew and JTB versus a voltage-controlled oscillator tuning range required for 1 unit interval deskew), the proposed receiver makes them independent. Therefore, the proposed receiver can achieve the optimal JTB in a wide range by controlling deskew phase and JTB independently. A test chip was implemented to prove 11Gb/s data recovery with constant 70MHz to 1GHz JTB in 0.13μm CMOS.

Related paper: "A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth" by Sang-Hye Chung

Wongyu Shin, Jeongmin Yang, and Jungwhan Choi (Advisor Lee-Sup Kim) received “Best Paper Runner-Up Award” in HPCA 2014.

Related paper: "NUAT: A Non-Uniform Access Time Memory Controller" by Wongyu Shin

Latest News

July 31, 2017

설호석씨의 논문이 TVLSI에 accept 되었습니다.
*제목: In-DRAM data initialization
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July 1, 2017

우리 연구실에서 강원도 정선으로 여름 MT를 다녀왔습니다.
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June 29, 2017

정종수씨가 IDEC SoC Congress Chip Design Contest에서 Best Design Award를 수상하였습니다.
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May 13, 2017

5월 13일에 연구실 홈커밍데이 행사가 있었습니다.
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May 6, 2017

최명훈씨의 논문이 The International Symposium on Low Power Electronics and Design 에 게재 승인 되었습니다.
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April 6, 2017

최영재씨의 논문이 IEEE Transactions on Circuits and Systems에 게재 승인 되었습니다.
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March 8, 2017

김현욱씨의 논문이 ACM/IEEE Design Automation Conference에 게재 승인 되었습니다.
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Feb. 17, 2017

2017년 졸업식이 있었습니다.
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Feb. 7, 2017

2017년 연구실 신입생 환영회 및 졸업생 송별회가 있었습니다.
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Feb. 3, 2017

신원규씨의 논문이 TC에 게재 승인 되었습니다.
*제목: : Bank-Group Level Parallelism
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Recently Accepted Papers

Journal (to be published)

Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim
In-DRAM data initialization
IEEE Transactions on Very Large Scale Integration Systems, 2017
 
Yeongjae Choi, Dongmyung Bae, Jaehyeong Sim, Seungkyu Choi, Minhye Kim, Lee-Sup Kim
Energy-efficient design of processing element for convolutional neural network
IEEE Transactions on Circuits and Systems II, 2017
 

Conference (to be presented)

Myunghoon Choi, Seungkyu Choi, Jaehyeong Sim, Lee-Sup Kim
SENIN: An Energy-Efficient Sparse Neuromorphic System
The International Symposium on Low Power Electronics and Design , 2017