- Award
IDEC 우수참여교수상 - Award
2019 IDEC Congress Chip Design Contest Best Design Award - Award
2019 IDEC Congress Chip Design Contest Best Poster Award - Award
2017 IDEC SoC Congress Chip Design Contest Best Design Award - Research
ISSCC 2016 CNN Chip Featured in IEEE Spectrum April 2016 Issue
Lee-sup Kim received "우수참여교수상" in 2019 IDEC Congress Chip Design Contest.
Hyeon-ho Kim received "Best Design Award" in 2019 IDEC Congress Chip Design Contest.
Seung-kyu Choi received "Best Poster Award" in 2019 IDEC Congress Chip Design Contest.
Chong-soo Jung, Dong-il Lee and Dae-woong Lee(Advisor Lee-Sup Kim) received “Best Design Award” in 2017 IDEC SoC Congress Chip Design Contest.
Related paper: "A DLL-based Reference-less CDR with ISI Jitter Reduction Scheme "
by Chongsoo Jung
Our Convolutional Neural Network(CNN) chip presented at ISSCC 2016 is covered in the article "Neural Networks on the Go" in the IEEE Spectrum April 2016 Issue.
Related paper: "A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems"
by Jaehyeong Sim
Latest News
Aug. 11, 2019
심재형씨의 논문이 IEEE Transactions on Very Large Scale Integration Systems에 게재 승인되었습니다. Read MoreJune 21, 2019
신혜인씨의 논문이 IEEE/ACM International Conference On Computer Aided Design 학회에 게재 승인되었습니다. Read MoreJune 21, 2019
정영범씨의 논문이 IEEE/ACM International Conference On Computer Aided Design 학회에 게재 승인되었습니다. Read MoreJune 21, 2019
김경한씨의 논문이 IEEE/ACM International Conference On Computer Aided Design 학회에 게재 승인되었습니다. Read MoreMay 14, 2019
위현욱씨의 논문이 ACM/IEEE International Symposium on Low Power Electronics and Design 학회에 게재 승인되었습니다. Read More
Video
Demonstration video of object classification from 32x32 input images using our CNN chip.Demonstration viedo of image classification from 28 x 28 handwritten digit images using FPGA.
Recently Accepted Papers
Journal (to be published)
| Jaehyeong Sim, Somin Lee, Lee-Sup Kim |
| An Energy Efficient Deep Convolutional Neural Network Inference Processor with Enhanced Output Stationary Dataflow in 65nm CMOS |
| IEEE Transactions on Very Large Scale Integration Systems, 2019 |
Conference (to be presented)
| Hyein Shin, Jaehyeong Sim, Daewoong Lee, Lee-Sup Kim |
| A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks |
| IEEE/ACM International Conference On Computer Aided Design, 2019 |
| Youngbeom Jung, Yeongjae Choi, Jaehyeong Sim, Lee-Sup Kim |
| eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators |
| IEEE/ACM International Conference On Computer Aided Design, 2019 |
| Kyeonghan Kim, Hyein Shin, Jaehyeong Sim, Myeonggu Kang, Lee-Sup Kim |
| An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM |
| IEEE/ACM International Conference On Computer Aided Design, 2019 |
| Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Yeongjae Choi, Hyeonuk Kim, Lee-Sup Kim |
| A 47.4uJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices |
| IEEE Asian Solid-State Circuits Conference, 2019 |
