A weak ILO enables near-constant JTB.

Presented at VLSI 2011 by Sang-Hye Chung

This paper presents a forwarded-clock I/O receiver with wide range constant jitter tracking bandwidth (JTB). A JTB interpolator in the receiver enables wide JTB using a weak injection-locked oscillator (ILO) instead of a strong ILO, so narrow VCO tuning is possible. By using the JTB interpolator, the proposed receiver compensates for the JTB reduction caused by deskew-JTB dependency in conventional ILOs. An 8Gb/s receiver has been implemented to verify 70M~1GHz constant JTB and one UI deskew with only 1.94~2GHz VCO tuning. The 0.13um test chip consumes 17.2~21.4mW and occupies 0.04mm2. Keywords: Source synchronous link, injection-locked oscillator, receiver.

Multimedia Processor on Si-Interposer platform

Presented at ISSCC 2011 by Hyo-Eun Kim

A multimedia processor embedding a reconfigurable transceiver pool is presented for IC-Stacking on Si-interposer. Configurable vector processing units for frame-level parallelism, a unified filtering unit with memory-access-efficient texturing algorithm, and a programmable shader integrating multiple cores are used to achieve 140GOPS/W, 5.8GFLOPS/W in full operation. This processor achieves 1.7x higher frame rate, 8x higher memory bandwidth compared to the previous design by using architecture/circuit-level performance/energy optimization and IC-Stacking technology. The proposed filtering unit and algorithm reduces the energy-delay-product 83.8% compared to the previous design. The proposed graphics core architecture reduces the execution latency by 53% compared to the conventional SIMD architecture.

Mobile Ray Tracing Processor

Accepted in JSSC (Feb. 2012) by Hong-Yun Kim

This processor presents a mobile ray tracing processor (MRTP) with reconfigurable stream multi-processors (RSMPs) for high datapath utilization. The MRTP includes three RSMPs that operate in multiple instruction multiple data (MIMD) mode asynchronously to exploit instruction-level parallelism. Each RSMP is based on single instruction multiple thread (SIMT) architecture to exploit thread-level parallelism. An RSMP consists of twelve scalar processing elements (SPEs) that run multiple threads in parallel synchronously. A low datapath utilization caused by a branch divergence is improved by 19.9% on average by reconfiguring twelve SPEs between scalar and vector SIMT with 0.1% area overheads. MRTP achieves a peak performance of 673K rays per second while consuming 156mW at 100MHz with VDD=1.2V

Adaptive Equalizer

Accepted in TVLSI (2012) by Won-Young Lee

An adaptive equalizer with the capacitance multiplication for DisplayPort main link has been proposed. The proposed equalizing filter is based on Miller’s theorem and composed of MIM capacitors and a sub-amplifier. The active source degeneration capacitor achieves low cost and area saving with the capacitance multiplication. The equalizer satisfies the specification of DisplayPort version 1.1a. The measured eye widths of 2.7 Gb/s data are 0.6 UI and 0.5 UI for 5 m and 8 m cables, respectively. The core area is 286×380 μm2 and power consumption is 22.3 mW at 2.7 Gb/s at 1.8 V.

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Recently Accepted Papers

Journal (to be published)

Jae-Sung Yoon, Jeonghyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim

A Unified Graphics and Vision Processor with a 0.89µW/fps Pose Estimation Engine for Augmented Reality

IEEE Transactions on Very Large Scale Integration Systems, 2012

Hyo-Eun Kim, Jae-Sung Yoon, Kyu-Dong Hwang, Young-Jun Kim, Jun-Seok Park, Lee-Sup Kim

A Reconfigurable Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer

IEEE Transactions on Circuits and Systems for Video Technology, 2011

Young-Jun Kim, Hyo-Eun Kim, Seok-Hoon Kim, Jun-Seok Park, Seungwook Paek, Lee-Sup Kim

Homogeneous Stream Processors with Embedded Special Function Units for High-Utilization Programmable Shaders

IEEE Transactions on Very Large Scale Integration Systems, 2011

Seok-Hoon Kim, Sang-Hye Chung, Young-Jun Kim, Hong-Yun Kim, Kyusik Chung, Lee-Sup Kim

A Mobile 3D Display Processor with A Bandwidth-Saving Subdivider

IEEE Transactions on Very Large Scale Integration Systems, 2011

Won-Young Lee, Lee-Sup Kim

An Adaptive Equalizer with the Capacitance Multiplication for DisplayPort Main Link in 0.18 μm CMOS Logic Process

IEEE Transactions on Very Large Scale Integration Systems, 2011

Conference (to be presented)

Yong-Hun Kim, Lee-Sup Kim

A 20 Gbps 1-Tap Decision Feedback Equalizer with Unfixed Tap Coefficient

IEEE International Symposium on Circuits and Systems, 2012

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