Our Convolutional Neural Network(CNN) chip presented at ISSCC 2016 is covered in the article "Neural Networks on the Go" in the IEEE Spectrum April 2016 Issue.

Related paper: "A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems" by Jaehyeong Sim

Yong-Hun Kim, Young-Ju Kim, and Tae-Ho Lee (Advisor Lee-Sup Kim) received “Best Design Award” in 2014 IDEC SoC Congress Chip Design Contest.

Related paper: "A 21Gb/s, 1.63pJ/bit Adaptive CTLE and 1-tap DFE with Single Loop Spectrum Balancing Method in 65nm CMOS" by Yong-Hun Kim

Jaehyeong Sim, Jun-Seok Park, and Seungwook Paek (Advisor Lee-Sup Kim) received “Best Paper Award” in The 32nd IEEE International Conference on Computer Design.

Related paper: "Timing Error Masking by Exploiting Operand Value Locality in SIMD Architecture" by Jaehyeong Sim

A source synchronous architecture with constant and wide jitter-tracking bandwidth (JTB) is presented. The proposed receiver is based on an injection-locked oscillator (ILO), which provides jitter filtering and phase deskew simultaneously. While using only the ILO has intrinsic two dependence problems (JTB versus deskew and JTB versus a voltage-controlled oscillator tuning range required for 1 unit interval deskew), the proposed receiver makes them independent. Therefore, the proposed receiver can achieve the optimal JTB in a wide range by controlling deskew phase and JTB independently. A test chip was implemented to prove 11Gb/s data recovery with constant 70MHz to 1GHz JTB in 0.13μm CMOS.

Related paper: "A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth" by Sang-Hye Chung