Jitter Filtering in Forwarded-Clock Architecture

As time goes on, global markets require a higher speed of a communication in microprocessor I/O (Figure 1). To increase the speed of a communication between semiconductor chips, designers typically sacrifice power consumption. However, since there is a tradeoff between a high speed communication and power consumption, and the global markets require low power consumption for mobile world as well, we should achieve both a high frequency communication speed and low power consumption simultaneously in spite of the tradeoff.

Figure 2 shows typically used two kinds of I/O transceivers; an embedded-clock architecture (ECA) and a forwarded-clock architecture (FCA). The main difference between two architectures is whether transmitting clocks through channels or not. Since ECA does not require additional channels for the clock transmission, it has an advantage of smaller cost than FCA. However, it requires complex circuits for dynamic clock recovery, which directly related to high power consumption. Instead, FCA can achieve a high speed communication with a simple architecture and low power consumption in virtue of transmitting both data and clocks by using the same clock generator. Based on the market trend, we are now focusing on the research about FCA.